libElysianVMU 1.6.0
Full-featured, accurate, cross-platform library emulating the Dreamcast's Visual Memory Unit
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Instruction Set

Listing of all LC86K instructions and their details.

0 1 2-3 4-7 8-F
0 NOP BR r8 LD d9 LD @Ri CALL a12
1 CALLR r16 BRF r16 ST d9 ST @Ri
2 CALLF a16 JMPF a16 MOV #i8, d9 MOV #i8, @Ri JMP a12
3 MUL BE #i8, r8 BE d9, r8 BE @Ri, #i8, r8
4 DIV BNE #i8, r8 BNE d9, r8 BNE @Ri, #i8, r8 BPC d9, b3, r8
5 LDF STF DBNZ d9, r8 DBNZ @Ri, r8
6 PUSH d9 INC d9 INC @Ri BP d9, b3, r8
7 POP d9 DEC d9 DEC @Ri
8 BZ r8 ADD #i8 ADD d9 ADD @Ri BN d9, b3, r8
9 BNZ r8 ADDC #i8 ADDC d9 ADDC @Ri
A RET SUB #i8 SUB d9 SUB @Ri NOT1 d9, b3
B RETI SUBC #i8 SUBC d9 SUBC @Ri
C ROR LDC XCH d9 XCH @Ri CLR1 d9, b3
D RORC OR #i8 OR d9 OR @Ri
E ROL AND #i8 AND d9 AND @Ri SET1 d9, b3
F ROLC XOR #i8 XOR d9 XOR @Ri

The LC86K instruction set has 70 instructions, which are identified by 45 operation codes. These opcodes can be grouped into 8 categories.

Arithmetic

ADD

Add the operand to the ACC Register. CY, AC, and OV are all affected depending on the result.

Mnemonic Encoding Cycles
ADD #i8 10000001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
ADD d9 1000001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
ADD @Ri 100001[i1][i0] 1

ADDC

Add the operand plus the carry bit (CY) to the ACC Register. CY, AC, and OV are all affected depending on the result.

Mnemonic Encoding Cycles
ADDC #i8 10010001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
ADDC d9 1001001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
ADDC @Ri 100101[i1][i0] 1

SUB

Subtract the operand from the ACC Register. CY, AC, and OV are all affected depending on the result.

Mnemonic Encoding Cycles
SUB #i8 10100001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
SUB d9 1010001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
SUB @Ri 101001[i1][i0] 1

SUBC

Subtract the operand and carry flag (CY) from the ACC Register. CY, AC, and OV are all affected depending on the result.

Mnemonic Encoding Cycles
SUBC #i8 10110001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
SUBC d9 1011001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
SUBC @Ri 101101[i1][i0] 1

INC

Add 1 to the operand. No PSW flags are affected.

Mnemonic Encoding Cycles
INC d9 0110001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
INC @Ri 011001[i1][i0] 1

DEC

Subtract 1 from the operand. No PSW flags are affected.

Mnemonic Encoding Cycles
DEC d9 0111001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
DEC @Ri 011101[i1][i0] 1

MUL

The 16-bit operand formed by the value of ACC being the high 8-bits and the value of C being the low 8-bits is multiplied by the value of the B register. The resulting 24-bit integer is stored from the high to low byte within B, ACC, and C respectively. CY is cleared. OV is set if the result is greater than 16-bits or cleared otherwise.

Mnemonic Encoding Cycles
MUL 00110000 7

DIV

The 16-bit operand formed by the value of ACC being the high 8-bits and the value of C being the low 8-bits is divided by the contets of the B register. The resulting 16-bit quotient has its high byte stored within ACC and its low byte within C. The remainder is stored within B. CY is clared. OV is set if the remainder is zero or is cleared otherwise.

Mnemonic Encoding Cycles
DIV 01000000 7

Logical

AND

Perform bitwise AND operation between the contents of the ACC register and the given operand. No PSW flags are modified.

Mnemonic Encoding Cycles
AND #i8 11100001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
AND d9 1110001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
AND @Ri 111001[i1][i0] 1

OR

Perform bitwise OR operation between the contents of the ACC register and the given operand. No PSW flags are modified.

Mnemonic Encoding Cycles
OR #i8 11010001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
OR d9 1101001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
OR @Ri 110101[i1][i0] 1

XOR

Perform bitwise XOR operation between the contents of the ACC register and the given operand. No PSW flags are modified.

Mnemonic Encoding Cycles
XOR #i8 11110001 [i7][i6][i5][i4][i3][i2][i1][i0] 1
XOR d9 1111001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
XOR @Ri 111101[i1][i0] 1

ROL

Rotate the value of the ACC register to the left by one bit position, wrapping the most significant bit around to the least significant bit. No PSW flags are modified.

Mnemonic Encoding Cycles
ROL 11100000 1

ROLC

Rotate the value of the ACC register to the left by one bit position, copying the most significant bit to the CY flag, and replacing the least significant bit with the old value of the CY flag. AV and OC flags are not modified.

Mnemonic Encoding Cycles
ROLC 11110000 1

ROR

Rotate the value of the ACC register to the right by one bit position, wrapping the least significant bit around to the most significant bit. No PSW flags are modified.

Mnemonic Encoding Cycles
ROR 11000000 1

RORC

Rotate the value of the ACC register to the right by one bit position, copying the least significant bit to the CY flag, and replacing the most significant bit with the old value of the CY flag. AV and OC flags are not modified.

Mnemonic Encoding Cycles
RORC 11010000 1

Data Transfer

LD

Load the operand into the ACC register. No PSW flags are modified.

Mnemonic Encoding Cycles
LD d9 0000001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
LD @Ri 000001[i1][i0] 1

ST

Store the value held in the ACC register into the operand address. No PSW flags are modified.

Mnemonic Encoding Cycles
ST d9 0001001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
ST @Ri 000101[i1][i0] 1

MOV

Sets the operand value to the immediate value. No PSW flags are modified

Mnemonic Encoding Cycles
MOV @i8, d9 0010001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] [i7][i6][i5][i4][i3][i2][i1][i0] 2
MOV #i8, @Rj 001001[i1][i0] [i7][i6][i5][i4][i3][i2][i1][i0] 1

LDC

Loads a value from instruction space into the ACC register. The source address is calculated by adding ACC to the 16-bit table register value (TRH being the high byte, TRL being the low byte). No PSW flags are modified

Mnemonic Encoding Cycles
LDC 11000001 2

LD

Loads a value directly from flash into the ACC register. The flash address is given by the 17-bit value created by combining the low table register value as the lowest byte, the high table register value as the second byte, and using the value of FPR.addr (bit 0) as the 16th bit.

Mnemonic Encoding Cycles
LDF 01010000 2
Warning
This is only supposed to be done from the BIOS in system mode and bypasses any flash protection routines handled by Sega/Sanyo.

STF

Stores the value in the ACC register directly to flash. The flash address is given by the 17-bit value created by combining the low table register value as the lowest byte, the high table register value as the second byte, and using the value of FPR.addr (bit 0) as the 16th bit.

Mnemonic Encoding Cycles
STF 01010001 2
Note
This call will only succeed when flash has been programmed with the proper unlock sequence
Warning
This is only supposed to be done from the BIOS in system mode and bypasses any flash protection routines handled by Sega/Sanyo.

PUSH

Pushes the operand onto the stack by incrementing the SP by one and storing it at the resulting position. No PSW flags are modified.

Mnemonic Encoding Cycles
PUSH d9 0110000[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 2

POP

Pops the operand from the stack by reading its value from the position pointed to by the SP register, then decrementing it by 1. No PSW flags are modified.

Mnemonic Encoding Cycles
POP d9 0111000[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 2

XCH

Echanges the values of the operand and the ACC register. No PSW flags are modified.

Mnemonic Encoding Cycles
XCH d9 1100000[d8] [d7][d6][d5][d4][d3][d2][d1][d0] 1
XCH @Ri 110001[i1][i0] 1

Jump

JMP

Jump unconditionally to the specified 12-bit absolute address. The upper 4 bits of this address must match with the instruction following the JMP. No PSW flags are modified.

Mnemonic Encoding Cycles
JMP a12 001[a11]1[a10][a9][a8] [a7][a6][a5][a4][a3][a2][a1][a0] 2

JMPF

Far jump unconditionally to the specified 16-bit absolute address. No PSW flags are modified.

Mnemonic Encoding Cycles
JMPF a16 00100001 [a15][a14][a13][a12][a11][a10][a9][a8] [a7][a6][a5][a4][a3][a2][a1][a0] 2

BR

Branch unconditionally to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BR. No PSW flags are modified.

Mnemonic Encoding Cycles
BR r8 00000001 [r7][r6][r5][r4][r3][r2][r1][r0] 2

BRF

Far branch unconditionally to the 16-bit relative address, which is added as a 16-bit unsigned offset to the address of the instruction following the BRF minus one. Since the PC is a 16-bit unsigned integer, the operation can overflow 65536 and wrap back around, meaning you can branch to a lower address as well. No PSW flags are modified.

Mnemonic Encoding Cycles
BRF r16 00010001 [r7][r6][r5][r4][r3][r2][r1][r0] [r15][r14][r13][r12][r11][r10][r9][r8] 4

Conditional Branch

BZ

Branch if the ACC register is zero to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BZ. No PSW flags are modified.

Mnemonic Encoding Cycles
BZ r8 10000000 [r7][r6][r5][r4][r3][r2][r1][r0] 2

BNZ

Branch if the acc register is not zero to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following BNZ. No PSWflags are modified.

Mnemonic Encoding Cycles
BNZ r8 10010000 [r7][r6][r5][r4][r3][r2][r1][r0] 2

BP

Branch if the specified bit of the operand is set, to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BP. No PSW flags are modified.

Mnemonic Encoding Cycles
BP d9, b3, r8 011[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

BPC

If the specified bit of the operand is set, clear the bit and branch to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BPC. No PSW flags are modified.

Mnemonic Encoding Cycles
BPC d9, b3, r8 010[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

BN

Branch if the specified bit of the operand is not set, to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BN. No PSW flags are modified.

Mnemonic Encoding Cycles
BN d9, b3, r8 100[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

DBNZ

Decrements the operand by one, branching if the result is not zero to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BN. No PSW flags are modified.

Mnemonic Encoding Cycles
DBNZ d9, r8 0101001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2
DBNZ @Ri, r8 010101[i1][i0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

BE

Branch if the value of the ACC register (or the indirect operand in the case of indirect addressing) is equal to the immediate or direct operand. CY is set 1 if ACC (or the indirect operand) is less than (but not equal to) the immediate or direct operand. AC and OV are not modified.

Mnemonic Encoding Cycles
BE #i8, r8 00110001 [i7][i6][i5][i4][i3][i2][i1][i0] [r7][r6][r5][r4][r3][r2][r1][r0] 2
BE d8, r8 0011001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2
BE @Ri, #i8, r8 001101[i1][i0] [i7][i6][i5][i4][i3][i2][i1][i0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

BNE

Branches if the contents of the ACC register (or the indirect operand as with the indirect addressing mode) are not equal to the immediate or direct operand, to the 8-bit relative address, which is added as an 8-bit signed offset to the address of the instruction following the BE. No PSW flags are modified.

Mnemonic Encoding Cycles
BNE #i8, r8 01000001 [i7][i6][i5][i4][i3][i2][i1][i0] [r7][r6][r5][r4][r3][r2][r1][r0] 2
BNE d8, r8 0100001[d8] [d7][d6][d5][d4][d3][d2][d1][d0] [r7][r6][r5][r4][r3][r2][r1][r0] 2
BNE @Ri, #i8, r8 010001[i1][i0] [i7][i6][i5][i4][i3][i2][i1][i0] [r7][r6][r5][r4][r3][r2][r1][r0] 2

Subroutine

CALL

Calls a function at the entry address specified using the 12-bit absolute address. The upper 4 bits of the address must be the same as the instruction following the CALL. The return address (address of the instruction following the CALL) is pushed onto the stack, with the lower 8-bits of the address pushed first, followed by the upper 8-bits. No PSW flags are modified.

Mnemonic Encoding Cycles
CALL a12 000[a11]1[a10][a9][a8] [a7][a6][a5][a4][a3][a2][a1][a0] 2

CALLF

Makes a far call to a function at the entry address specified using a full 16-bit absolute address. The return address (address of the instruction following the CALLF) is pushed onto the stack, with the lower 8-bits of the address pushed first, followed by the upper 8-bits. No PSW flags are modified.

Mnemonic Encoding Cycles
CALLF a16 00100000 [a15][a14][a13][a12][a11][a10][a9][a8] [a7][a6][a5][a4][a3][a2][a1][a0] 2

CALLR

Calls a function whose entry-point is specified as the 16-bit relative address operand. The address is calculated by adding the unsigned 16-bit offset to the address of the next instruction, proceeding the CALLR, minus one to produce the target address. Since the PC is a 16-bit unsigned integer, this can overflow and wrap back around, allowing you to call to lower addresseses as well. The return address (the instruction after the CALLR) is pushed onto the stack, with the lower byte being pushed first followed by the upper byte. No PSW flags are modified.

Mnemonic Encoding Cycles
CALLR r16 00010000 [r7][r6][r5][r4][r3][r2][r1][r0] [r8][r9][r10][r11][r12][r13][r14][r15] 4

RET

Returns from a function, popping the PC from the stack, with the upper byte being popped first, followed by the lower byte. No PSW flags are modified.

Mnemonic Encoding Cycles
RET 10100000 2

RETI

Returns from an interrupt, popping the PC from the stack, with the upper byte being popped first, followed by the lower byte. No PSW flags are modified.

Mnemonic Encoding Cycles
RETI 10110000 2

Bit Manipulation

CLR1

Clears the specified bit in within the operand. No PSW flags are modified.

Mnemonic Encoding Cycles
CLR1 d9, b3 110[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] 1

SET1

Sets the specified bit in within the operand. No PSW flags are modified.

Mnemonic Encoding Cycles
SET1 d9, b3 111[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] 1

NOT1

Clears the specified bit in within the operand. No PSW flags are modified.

Mnemonic Encoding Cycles
NOT1 d9, b3 101[d8]1[b2][b1][b0] [d7][d6][d5][d4][d3][d2][d1][d0] 1

Miscellaneous

NOP

Does nothing. No PSW flags are modifed.

Mnemonic Encoding Cycles
NOP 00000000 1