Interrupt Service Routines

Macros
#define	EVMU_ISR_ADDR_RESET   0x00
#define	EVMU_ISR_ADDR_EXT_INT0   0x03
#define	EVMU_ISR_ADDR_EXT_INT1   0x0b
#define	EVMU_ISR_ADDR_EXT_INT2_T0L   0x13
#define	EVMU_ISR_ADDR_EXT_INT3_TBASE   0x1b
#define	EVMU_ISR_ADDR_T0H   0x23
#define	EVMU_ISR_ADDR_T1   0x2b
#define	EVMU_ISR_ADDR_SIO0   0x33
#define	EVMU_ISR_ADDR_SIO1   0x3b
#define	EVMU_ISR_ADDR_RFB   0x43
#define	EVMU_ISR_ADDR_P3   0x4b
#define	EVMU_ISR_ADDR_11   0x4f
#define	EVMU_ISR_ADDR_12   0x52
#define	EVMU_ISR_ADDR_13   0x55
#define	EVMU_ISR_ADDR_14   0x5a
#define	EVMU_ISR_ADDR_15   0x5d

Detailed Description

Entry addresses for each interrupt.

Macro Definition Documentation

EVMU_ISR_ADDR_11

#define EVMU_ISR_ADDR_11   0x4f

#include <evmu_pic.h>

ISR 11 Address (undocumented/unused?)

Definition at line 48 of file evmu_pic.h.

EVMU_ISR_ADDR_12

#define EVMU_ISR_ADDR_12   0x52

#include <evmu_pic.h>

ISR 12 Address (undocumented/unused?)

Definition at line 49 of file evmu_pic.h.

EVMU_ISR_ADDR_13

#define EVMU_ISR_ADDR_13   0x55

#include <evmu_pic.h>

ISR 13 Address (undocumented/unused?)

Definition at line 50 of file evmu_pic.h.

EVMU_ISR_ADDR_14

#define EVMU_ISR_ADDR_14   0x5a

#include <evmu_pic.h>

ISR 14 Address (undocumented/unused?)

Definition at line 51 of file evmu_pic.h.

EVMU_ISR_ADDR_15

#define EVMU_ISR_ADDR_15   0x5d

#include <evmu_pic.h>

ISR 15 Address (undocumented/unused?)

Definition at line 52 of file evmu_pic.h.

EVMU_ISR_ADDR_EXT_INT0

#define EVMU_ISR_ADDR_EXT_INT0   0x03

#include <evmu_pic.h>

INT0 interrupt (external) ISR address.

Definition at line 38 of file evmu_pic.h.

EVMU_ISR_ADDR_EXT_INT1

#define EVMU_ISR_ADDR_EXT_INT1   0x0b

#include <evmu_pic.h>

INT1 interrupt (external) ISR address.

Definition at line 39 of file evmu_pic.h.

EVMU_ISR_ADDR_EXT_INT2_T0L

#define EVMU_ISR_ADDR_EXT_INT2_T0L   0x13

#include <evmu_pic.h>

INT2 interrupt (external) or T0L overflow ISR address.

Definition at line 40 of file evmu_pic.h.

EVMU_ISR_ADDR_EXT_INT3_TBASE

#define EVMU_ISR_ADDR_EXT_INT3_TBASE   0x1b

#include <evmu_pic.h>

INT3 interrupt (external) or Base Timer overflow ISR address.

Definition at line 41 of file evmu_pic.h.

EVMU_ISR_ADDR_P3

#define EVMU_ISR_ADDR_P3   0x4b

#include <evmu_pic.h>

P3 interrupt ISR address.

Definition at line 47 of file evmu_pic.h.

EVMU_ISR_ADDR_RESET

#define EVMU_ISR_ADDR_RESET   0x00

#include <evmu_pic.h>

Reset ISR address.

Definition at line 37 of file evmu_pic.h.

EVMU_ISR_ADDR_RFB

#define EVMU_ISR_ADDR_RFB   0x43

#include <evmu_pic.h>

RFB interrupt (VMU<->VMU receive/detect) ISR address.

Definition at line 46 of file evmu_pic.h.

EVMU_ISR_ADDR_SIO0

#define EVMU_ISR_ADDR_SIO0   0x33

#include <evmu_pic.h>

SIO0 ISR address.

Definition at line 44 of file evmu_pic.h.

EVMU_ISR_ADDR_SIO1

#define EVMU_ISR_ADDR_SIO1   0x3b

#include <evmu_pic.h>

SI01 ISR address.

Definition at line 45 of file evmu_pic.h.

EVMU_ISR_ADDR_T0H

#define EVMU_ISR_ADDR_T0H   0x23

#include <evmu_pic.h>

T0H overflow ISR address.

Definition at line 42 of file evmu_pic.h.

EVMU_ISR_ADDR_T1

#define EVMU_ISR_ADDR_T1   0x2b

#include <evmu_pic.h>

T1H or T1L overflow ISR address.

Definition at line 43 of file evmu_pic.h.